Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 547
1: Channel status A&B generated form TX_CHSTA
0
R/W
0
TXEN
0: disabled
1: enabled
8.7.4.3. OWA RX Configure Register(Default Value: 0x00000000)
Offset: 0x08
Register Name: OWA_RX_CFIG
Bit
R/W
Default/Hex
Description
31:5
/
/
/
4
R
0
RX_LOCK_FLAG
0: unlock
1: lock
3
R/W
0
RX_CHST_SRC
0: RX_CH_STA Register holds status from Channel A
1: RX_CH_STA Register holds status from Channel B
2
/
/
/
1
R/W
0
CHST_CP
Channel status Capture
0: Idle or capture end
1: Capture Channel status start
Notes: When set to ‘1’, the channel status information is capturing, the bit
will clear to ‘0’ after captured.
0
R/W
0
RXEN
0: disabled
1: enabled
8.7.4.4. OWA Interrupt Status Register(Default Value: 0x00000010)
Offset: 0x0C
Register Name: OWA_ISTA
Bit
R/W
Default/Hex
Description
31:19
/
/
/
18
R/W
0
RX_LOCK_INT
0: No pending IRQ
1: RX lock Pending Interrupt (RX_LOCK_FLAG 0→1)
Write “1” to clear this interrupt
17
R/W
0
RX_UNLOCK_INT
RX Unlock Pending Interrupt
0: No pending IRQ
1: RX Unlock Pending Interrupt (RX_LOCK_FLAG 1→0)
Write “1” to clear this interrupt
16
R/W
0
RX_PARERRI_INT
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