Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 548
RX Parity Error Pending Interrupt
0: No pending IRQ
1: RX Parity Error Pending Interrupt
Write “1” to clear this interrupt
15:7
/
/
/
6
R/W
0
TXU_INT
TX FIFO Under run Pending Interrupt
0: No pending IRQ
1: FIFO Under run Pending Interrupt
Write “1” to clear this interrupt
5
R/W
0
TXO_INT
TX FIFO Overrun Pending Interrupt
0: No Pending IRQ
1: FIFO Overrun Pending Interrupt
Write “1” to clear this interrupt
4
R/W
1
TXE_INT
TX FIFO Empty Pending Interrupt
0: No Pending IRQ
1: FIFO Empty Pending Interrupt
Write “1” to clear this interrupt or automatically clear if interrupt condition
fails.
3:2
/
/
/
1
R/W
0
RXO_INT
RX FIFO Overrun Pending Interrupt
0: FIFO Overrun Pending
Write “1” to clear this interrupt
0
R/W
0
RXA_INT
RX FIFO Available Pending Interrupt
0: No Pending IRQ
1: Data Available Pending IRQ
Write “1” to clear this interrupt or automatically clear if interrupt condition
fails
8.7.4.5. OWA RX FIFO Register(Default Value: 0x00000000)
Offset: 0x10
Register Name: OWA_RXFIFO
Bit
R/W
Default/Hex
Description
31:0
R
0
RX_DATA
Host can get one sample by reading this register, the A channel data is first
and then the B channel data
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