Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 549
8.7.4.6. OWA FIFO Control Register(Default Value: 0x00001078)
Offset: 0x14
Register Name: OWA_FCTL
Bit
R/W
Default/Hex
Description
31
R/W
0
HUB_EN
Audio hub enable
0 : Disable
1: Enable
30:18
/
/
/
17
R/W
0
FTX
Write “1” to flush TX FIFO, self clear to “0”
16
R/W
0
FRX
Write “1” to flush RX FIFO, self clear to “0”
15:13
/
/
/
12:8
R/W
0x10
TXTL
TX FIFO empty Trigger Level
Interrupt and DMA request trigger level for TX FIFO normal condition
Trigger Level = TXTL
7:3
R/W
0x0F
RXTL
RX FIFO Trigger Level
Interrupt and DMA request trigger level for RX FIFO normal condition
Trigger Level = RXTL + 1
2
R/W
0
TXIM
TX FIFO Input Mode(Mode0, 1)
0: Valid data at the MSB of OWA_TXFIFO register
1: Valid data at the LSB of OWA_TXFIFO register
Example for 20-bits transmitted audio sample:
Mode 0: FIFO_I[23:0] = {TXFIFO[31:12], 4’h0}
Mode 1: FIFO_I[23:0] = {TXFIFO[19:0], 4’h0}
1:0
R/W
0
RXOM
RX FIFO Output Mode(Mode 0,1,2,3)
00: Expanding “0” at LSB of SPDIP_RXFIFO register
01: Expanding received sample sign bit at MSB of OWA_RXFIFO register
10: Truncating received samples at high half-word of OWA_RXFIFO register
and low half-word of AC_FIFO register is filled by “0”
11: Truncating received samples at low half-word of OWA_RXFIFO register
and high half-word of AC_FIFO register is expanded by its sigh bit
Mode0: RXFIFO[31:0] = {FIFO_O[23:0], 8’h0}
Mode 1: RXFIFO[31:0] = {8’FIFO_O[23], FIFO_O[23:0]}
Mode 2: RXFIFO[31:0] = {FIFO_O[23:8], 16’h0}
Mode 3: RXFIFO[31:0] = {16’FIFO_O[23], FIFO_O[23:8]}
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