Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 551
0: Disable
1: Enable
5
R/W
0
TXOI_EN
TX FIFO Overrun Interrupt Enable
0: Disable
1: Enable
4
R/W
0
TXEI_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable
3
/
/
/
2
R/W
0
RX_DRQ
RX FIFO Data Available DRQ Enable
When set to “1”, RX FIFO DMA Request is asserted if Data is available in RX
FIFO
0: Disable
1: Enable
1
R/W
0
RXOI_EN
RX FIFO Overrun Interrupt Enable
0: Disable
1: Enable
0
R/W
0
RXAI_EN
RX FIFO Data Available Interrupt Enable
0: Disable
1: Enable
8.7.4.9. OWA TX FIFO Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: OWA_TXFIFO
Bit
R/W
Default/Hex
Description
31:0
W
0
TX_DATA
Transmitting A, B channel data should be written this register one by one.
The A channel data is first and then the B channel data.
8.7.4.10. OWA TX Counter Register(Default Value: 0x00000000)
Offset: 0x24
Register Name: OWA_TX_CNT
Bit
R/W
Default/Hex
Description
31:0
R/W
0
TX_CNT
TX Sample counter
The audio sample number of writing into TX FIFO. When one sample is
written by DMA or by host IO, the TX sample counter register increases by
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