Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 559
Smart Card Reader
APB
SCR
Registers
TX FIFO
RX FIFO
SCR
Clock
Generator
SCR
Controller
SCR
Interface
SCR_Det
SCR_Vpppp
SCR_Vppen
SCR_Vcc
SCR_Clk
SCR_Rst
SCR_IO
Figure 8-17. SCR Block Diagram
8.8.3. SCR Timing Diagram
Please refer ISO/IEC 7816 and EMV2000 Specification.
8.8.4. SCR Special Requirement
8.8.4.1. Clock Generator
The Clock Generator generates the Smart Card Clock signal and the Baud Clock Impulse signal, used in timing the Smart
Card Reader.
The Smart Card Clock signal is used as the main clock for the smart card. Its frequency can be adjusted using the Smart
Card Clock Divisor (SCCDIV). This value is used to divide the system clock. The SCCLK frequency is given by the following
equation:
2 * ( 1)
sy sc lk
sc clk
f
f
SC C D IV


sc c lk
f
-- Smart Card Clock Frequency
sysclk
f
-- System Clock (PCLK) Frequency
The Baud Clock Impulse signal is used to transmit and receive serial between the Smart Card Reader and the Smart
Card. The baud rate can be modified using the Baud Clock Divisor (BAUDDIV). The value is used to divide the system
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