Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 561
SCR_CSR
0x000
Smart Card Reader Control and Status Register
SCR_INTEN
0x004
Smart Card Reader Interrupt Enable Register 1
SCR_INTST
0x008
Smart Card Reader Interrupt Status Register 1
SCR_FCSR
0x00c
Smart Card Reader FIFO Control and Status Register
SCR_FCNT
0x010
Smart Card Reader RX and TX FIFO Counter Register
SCR_RPT
0x014
Smart Card Reader RX and TX Repeat Register
SCR_DIV
0x018
Smart Card Reader Clock and Baud Divisor Register
SCR_LTIM
0x01c
Smart Card Reader Line Time Register
SCR_CTIM
0x020
Smart Card Reader Character Time Register
SCR_LCTLR
0x030
Smart Card Reader Line Control Register
SCR_FIFO
0x100
Smart Card Reader RX and TX FIFO Access Point
8.8.6. SCR Register Description
8.8.6.1. Smart Card Reader Control and Status Register(Default Value: 0x00000000)
Offset: 0x00
Register Name: SCR_CSR
Bit
R/W
Default/Hex
Description
31
R
0
SCDET
Smart Card Detected
This bit is set to ‘1’ when the scdetect input is active at least for a
debounce time.
30
/
/
/
24
R/W
0
SCDETPOL
Smart Card Detect Polarity
This bit set polarity of scdetect signal.
0: Low Active
1: High Active
23:22
R/W
0
Protocol Selection (PTLSEL)
0x0 – T=0.
0x1 – T=1, no character repeating and no guard time is used when T=1
protocol is selected.
0x2 – Reserved
0x3 – Reserved
21
R/W
0
ATRSTFLUSH
ATR Start Flush FIFO
When enabled, both FIFOs are flushed before the ATR is started.
20
R/W
0
TSRXE
TS Receive Enable
When set to ‘1’, the TS character (the first ATR character) will be store in
RXFIFO during card session.
19
R/W
0
CLKSTPPOL
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