Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 562
Clock Stop Polarity
The value of the scclk output during the clock stop state.
18
R/W
0
PECRXE
Parity Error Character Receive Enable
Enables storage of the characters received with wrong parity in RX FIFO.
17
R/W
0
MSBF
MSB First
When high, inverse bit ordering convention (msb to lsb) is used.
16
R/W
0
DATAPOL
Data Plorarity
When high, inverse level convention is used (A=’1’, Z=’0’).
15:12
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11
R/W
0
DEACTDeactivation. Setting of this bit initializes the deactivation sequence.
When the deactivation is finished, the DEACT bit is automatically cleared.
10
R/W
0
ACT
Activation. Setting of this bit initializes the activation sequence. When the
activation is finished, the ACT bit is automatically cleared.
9
R/W
0
WARMRST
Warm Reset Command. Writing ‘1’ to this bit initializes Warm Reset of the
Smart Card. This bit is always read as ‘0’.
8
R/W
0
CLKSTOP
Clock Stop. When this bit is asserted and the smart card I/O line is in ‘Z’
state, the SCR core stops driving of the smart card clock signal after the
CLKSTOPDELAY time expires. The smart card clock is restarted immediately
after the CLKSTOP signal is deasserted. New character transmission can be
started after CLKSTARTDELAY time. The expiration of both times is signaled
by the CLKSTOPRUN bit in the interrupt registers.
7:3
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Reserved
2
R/W
0
GINTEN
Global Interrupt Enable. When high, IRQ output assertion is enabled.
1
R/W
0
RXEN
Receiving Enable. When enabled the characters sent by the Smart Card are
received by the UART and stored in RX FIFO. Receiving is internally disabled
while a transmission is in progress.
0
R/W
0
TXEN
Transmission Enable. When enabled the characters are read from TX FIFO
and transmitted through UART to the Smart Card.
8.8.6.2. Smart Card Reader Interrupt Enable Register(Default Value: 0x00000000)
Offset: 0x04
Register Name: SCR_INTEN
Bit
R/W
Default/Hex
Description
31:24
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