Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 565
RX FIFO Full Interrupt. When enabled, this interrupt is asserted if the RX
FIFO is filled up.
8
/
/
/
7:5
/
/
/
4
R/W
0
TXPERR
TX Parity Error Interrupt. When enabled, this interrupt is asserted if the
Smart Card signals wrong character parity during the guard time after the
character transmission was repeated TXREPEAT times or T=1 protocol is
used.
3
R/W
0
TXDONE
TX Done Interrupt. When enabled, this interrupt is asserted after one
character was transmitted to the smart card.
2
R/W
0
TXFIFOTHD
TX FIFO Threshold Interrupt. When enabled, this interrupt is asserted if the
number of bytes in TX FIFO is equal or less than the TX FIFO threshold.
1
R/W
0
TXFIFOEMPTY
TX FIFO Empty Interrupt. When enabled, this interrupt is asserted if the TX
FIFO is emptied out.
0
R/W
0
TXFIFODONE
TX FIFO Done Interrupt. When enabled, this interrupt is asserted after all
bytes from TX FIFO ware transferred to the Smart Card.
Note: This register provides information about the state of each interrupt bit. You can clear the register bits individually
by writing ‘1’ to a bit you intend to clear.
8.8.6.4. Smart Card Reader FIFO Control and Status Register(Default Value: 0x00000000)
Offset: 0x0C
Register Name: SCR_FCSR
Bit
R/W
Default/Hex
Description
31:11
/
/
/
10
R/W
0
RXFIFOFLUSH
Flush RX FIFO. RX FIFO is flushed, when ‘1’ is written to this bit.
9
R
0
RXFIFOFULL
RX FIFO Full.
8
R
1
RXFIFOEMPTY
RX FIFO Empty.
7:3
/
/
/
2
R/W
0
TXFIFOFLUSH
Flush TX FIFO. TX FIFO is flushed, when ‘1’ is written to this bit.
1
R
0
TXFIFOFULL
TX FIFO Full.
0
R
1
TXFIFOEMPTY
TX FIFO Empty.
confidential