Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 566
8.8.6.5. Smart Card Reader FIFO Counter Register(Default Value: 0x00000000)
Offset: 0x10
Register Name: SCR_FIFOCNT
Bit
R/W
Default/Hex
Description
31:24
R/W
0
RXFTH
RX FIFO Threshold
These bits set the interrupt threshold of RX FIFO. The interrupt is asserted
when the number of bytes it receives is equal to, or exceeds the threshold.
23:16
R/W
0
TXFTH
TX FIFO Threshold
These bits set the interrupt threshold of TX FIFO. The interrupt is asserted
when the number of bytes in TX FIFO is equal to or less than the threshold.
15:8
R
0
RXFCNT
RX FIFO Counter
These bits provide the number of bytes stored in the RXFIFO.
7:0
R
0
TXFCNT
TX FIFO Counter
These bits provide the number of bytes stored in the TXFIFO.
8.8.6.6. Smart Card Reader Repeat Control Register(Default Value: 0x00000000)
Offset: 0x14
Register Name: SCR_REPEAT
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:4
R/W
0
RXRPT
RX Repeat
This is a 4-bit register that specifies the number of attempts to request
character re-transmission after wrong parity was detected. The
re-transmission of the character is requested using the error signal during
the guard time.
3:0
R/W
0
TXRPT
TX Repeat
This is a 4-bit register that specifies the number of attempts to re-transmit
the character after the Smart Card signals the wrong parity during the
guard time.
8.8.6.7. Smart Card Reader Clock Divisor Register(Default Value: 0x00000000)
Offset: 0x18
Register Name: SCR_CLKDIV
Bit
R/W
Default/Hex
Description
31:16
R/W
0
BAUDDIV
Baud Clock Divisor. This 16-bit register defines the divisor value used to
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