Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 567
generate the Baud Clock impulses from the system clock.
2 * ( 1)
sy sc lk
f
B A U D
B A U D D IV


15:0
R/W
0
SCCDIV
Smart Card Clock Divisor. This 16-bit register defines the divisor value used
to generate the Smart Card Clock from the system clock.
2 * ( 1)
sy sc lk
sc clk
f
f
SC C D IV


scclk
f
is the frequency of Smart Card Clock Signal.
sysclk
f
is the frequency of APB Clock.
8.8.6.8. Smart Card Reader Line Time Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: SCR_LTIM
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23:16
R/W
0
ATR
ATR Start Limit. This 16-bit register defines the maximum time between the
rising edge of the scrstn signal and the start of ATR response.
ATR Start Limit = 128* ATR*
scclk
T
.
15:8
R/W
0
RST
Reset Duration. This 16-bit register sets the duration of the Smart Card
reset sequence. This value is same for the cold and warm reset.
Cold/Warm Reset Duration = 128* RST*
scclk
T
.
7:0
R/W
0
ACT
Activation/Deactivation Time. This 16-bit register sets the duration of each
part of the activation and deactivation sequence.
Activation/Deactivation Duration = 128* ACT *
scclk
T
.
1
scc lk
scc lk
T
f

is the Smart Card Clock Cycle.
8.8.6.9. Smart Card Reader Character Time Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: SCR_CTIM
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