Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 568
Bit
R/W
Default/Hex
Description
31:16
R/W
0
CHARLIMIT
Character Limit. This 16-bit register sets the maximum time between the
leading edges of two consecutive characters. The value is ETUs.
15:8
/
/
/
7:0
R/W
0
GUARDTIME
Character Guard time. This 8-bit register sets a delay at the end of each
character transmitted from the Smart Card Reader to the Smart Card. The
value is in ETUs. The parity error is besides signaled during the guard time.
8.8.6.10. Smart Card Reader Line Control Register(Default Value: 0x00000000)
Offset: 0x30
Register Name: SCR_PAD
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R/W
0
DSCVPPPP
Direct Smart Card Vpp Pause/Prog. It provides direct access to SCVPPPP
output.
6
R/W
0
DSCVPPEN
Direct Smart Card Vpp Enable. It provides direct access to SCVPPEN output.
5
R/W
0
AUTOADEAVPP
Automatic Vpp Handling. When high, it enables automatic handling of
DSVPPEN and DSVPPPP signals during activation and deactivation
sequence.
4
R/W
0
DSCVCC
Direct Smart Card VCC. When DIRACCPADS=’1’, the DSCVCC bit provides
direct access to SCVCC pad.
3
R/W
0
DSCRST
Direct Smart Card Clock. When DIRACCPADS=’1’, the DSCRST bit provides
direct access to SCRST pad.
2
R/W
0
DSCCLK
Direct Smart Card Clock. When DIRACCPADS=’1’, the DSCCLK bit provides
direct access to SCCLK pad.
1
R/W
0
DSCIO
Direct Smart Card Input/Output. When DIRACCPADS=’1’, the DSCIO bit
provides direct access to SCIO pad.
0
R/W
0
DIRACCPADS
Direct Access to Smart Card Pads. When high, it disables a serial interface
functionality and enables direct control of the smart card pads using
following 4 bits.
Note: This register provides direct access to smart card pads without serial interface assistance. You can use this register
feature with synchronous and any other non-ISO 7816 and non-EMV cards.
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