Owners manual

Overview

 16 address signal lines and 3 bank signal lines

 32-bits bus width

 Support clock frequency up to 667 MHz(DDR3-1333)

 Runtime-configurable parameters setting for application flexibility

 Random read or write operation is supported

2.1.3.3. NAND Flash

 Up to 2 flash chips

 8-bit data bus width

 Up to 64-bit ECC per 1024 bytes

 Support 1024, 2048, 4096, 8192, 16K bytes size per page

 Support SLC/MLC/TLC flash and EF-NAND memory

 Support SDR, ONFI DDR and Toggle DDR NAND

 Embedded DMA to do data transfer

 Support data transfer together with normal DMA

2.1.3.4. SD/MMC

 Up to three SD/MMC controller interfaces

 Comply to eMMC standard specification V4.41, SD physical layer specification V2.0, SDIO card specification V3.0

 1-bit or 4-bit data bus transfer mode for SD and SDIO cards up to 50MHz

 1-bit ,4-bit or 8-bit data bus transfer mode for MMC cards up to 50MHz in both SDR and DDR modes(100MB/s)

 Embedded special DMA to do data transfer

 Support SDIO suspend and resume operation

 Support hardware CRC generation and error detection

 Support SDIO interrupt detection

2.1.4. System Peripheral

2.1.4.1. Timer

 Two on-chip timers with interrupt-based operation

 One watchdogs to generate reset signal or interrupts

 33-bit Audio/Video Sync(AVS) Counter to synchronize video and audio in the player

 Input from Internal OSC and OSC24M

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