Owners manual

Interfaces

8.9. EMAC

8.9.1. Overview

The Ethernet MAC(EMAC) controller enables a host to transmit and receive data over Ethernet in compliance with

the IEEE 802.3-2002 standard. It supports 10M/100M/1000M external PHY with MII/ RGMII interface in both full

and half duplex mode. The Ethernet MAC-DMA is designed for packet-oriented data transfers based on a linked list

of descriptors. 4K Byte TXFIFO and 16K Byte RXFIFO are provided to keep continuous transmission and reception.

Flow Control, CRC Pad & Stripping, and address filtering are also supported in this module.

The Ethernet MAC Controller includes the following features:

 Supports 10/100/1000Mbps data transfer rates

 Supports MII/RGMII PHY interface

 Supports both full-duplex and half-duplex operation

 Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB

 Supports a variety of flexible address filtering modes

 Separate 32-bit status returned for transmission and reception packets

 Optimization for packet-oriented DMA transfers with frame delimiters

 Support linked-list (chained) descriptor chaining

 Descriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each

descriptor can transfer up to 4 KB of data

 Comprehensive status reporting for normal operation and transfers with errors

 4KB TXFIFO for transmission packets and 16KB RXFIFO for reception packets

 Programmable interrupt options for different operational conditions

8.9.2. Block Diagram

The EMAC Controller block diagram is shown below:

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