Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 571
EMAC
TXFIFO RXFIFO
TXFC RXFCDMA
DMA CSR
MAC CSR
OMR Register
AHB
Master
AHB Slave
MII
RGMII
PHY
Interface
RMII
Figure 8-19. EMAC Block Diagram
8.9.3. EMAC Core Register List
Module Name
Base Address
EMAC
0x01C30000
Register Name
Offset
Description
BASIC_CTL_0
0x00
Basic Control 0 Register
BASIC_CTL_1
0x04
Basic Control 1 Register
INT_STA
0x08
Interrupt Status Register
INT_EN
0x0C
Interrupt Enable Register
TX_CTL_0
0x10
Transmit Control 0 Register
TX_CTL_1
0x14
Transmit Control 1 Register
TX_FLOW_CTL
0x1C
Transmit Flow Control Register
TX_DMA_DESC_LIST
0x20
Transmit Descriptor List Address Register
RX_CTL_0
0x24
Receive Control 0 Register
RX_CTL_1
0x28
Receive Control 1 Register
RX_DMA_DESC_LIST
0x34
Receive Descriptor List Address Register
RX_FRM_FLT
0x38
Receive Frame Filter Register
RX_HASH_0
0x40
Hash Table 0 Register
RX_HASH_1
0x44
Hash Table 1 Register
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