Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 572
MII_CMD
0x48
Management Interface Command Register
MII_DATA
0x4C
Management Interface Data Register
ADDR_HIGH_0
0x50
MAC Address High Register 0
ADDR_LOW_0
0x54
MAC Address High Register 0
ADDR_HIGH_x
0x50+8*x
MAC Address High Register x(x:1~7)
ADDR_LOW_x
0x54+8*x
MAC Address Low Register x(x:1~7)
TX_DMA_STA
0xB0
Transmit DMA Status Register
TX_CUR_DESC
0xB4
Current Transmit Descriptor Register
TX_CUR_BUF
0xB8
Current Transmit Buffer Address Register
RX_DMA_STA
0xC0
Receive DMA Status Register
RX_CUR_DESC
0xC4
Current Receive Descriptor Register
RX_CUR_BUF
0xC8
Current Receive Buffer Address Register
RGMII_STA
0xD0
RGMII Status Register
8.9.4. EMAC Core Register Description
8.9.4.1. Basic Control 0 Register(Default Value: 0x00000000)
Offset: 0x00
Register Name: BASIC_CTL_0
Bit
R/W
Default/Hex
Description
31:4
/
/
/
3:2
R/W
0
SPEED
00: 1000Mbps
11: 100Mbps
10: 10Mbps
01: Reserved
1
R/W
0
LOOPBACK
0: Disable;
1: Enable;
0
R/W
0
DUPLEX
0: Half-duplex
1: Full-duplex
8.9.4.2. Basic Control 1 Register(Default Value: 0x08000000)
Offset: 0x04
Register Name: BASIC_CTL_1
Bit
R/W
Default/Hex
Description
31:30
/
/
/
confidential