Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 573
29:24
R/W
8
BURST_LEN
The burst length of RX and TX DMA transfer.
23:2
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1
R/W
0
RX_TX_PRI
0: RX DMA and TX DMA have same priority
1: RX DMA has priority over TX DMA
0
R/W
0
SOFT_RST
When this bit is set, soft reset all registers and logic. All clock inputs must be
valid before soft rest. This bit is cleared internally when the reset operation
is completed fully. Before write any register, this bit should read a 0.
8.9.4.3. Interrupt Status Register(Default Value: 0x00000000)
Offset: 0x08
Register Name: INT_STA
Bit
R/W
Default/Hex
Description
31:17
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16
R
0
RGMII_LINK_STA_INT
When this bit is asserted, the link status of RGMII interface is changed.
15:14
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13
R
0
RX_EARLY_INT
When this bit asserted, the RX DMA had filled the first data buffer of the
receive frame.
12
R
0
RX_OVERFLOW_INT
When this bit is asserted, the RX FIFO had an overflow error.
11
R
0
RX_TIMEOUT_INT
When this bit asserted, the length of receive frame is greater than 2048
bytes(10240 when JUMBO_FRM_EN is set)
10
R
0
RX_DMA_STOPPED_INT
When this bit asserted, the RX DMA FSM is stopped.
9
R
0
RX_BUF_UA _INT
When this asserted, the RX DMA can’t acquire next RX descriptor and RX
DMA FSM is suspended. The ownership of next RX descriptor should be
changed to RX DMA. The RX DMA FSM will resume when write to
DMA_RX_START bit or next receive frame is coming.
8
R
0
RX_INT
When this bit is asserted, a frame reception is completed. The RX DMA FSM
remains in the running state.
7:6
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5
R
0
TX_EARLY_INT
When this bit asserted , the frame is transmitted to FIFO totally.
4
R
0
TX_UNDERFLOW_INT
When this bit is asserted, the TX FIFO had an underflow error.
3
R
0
TX_TIMEOUT_INT
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