Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 574
When this bit is asserted, the transmitter had been excessively active.
2
R
0
TX_BUF_UA_INT
When this asserted, the TX DMA can not acquire next TX descriptor and TX
DMA FSM is suspended. The ownership of next TX descriptor should be
changed to TX DMA. The TX DMA FSM will resume when write to
DMA_TX_START bit.
1
R
0
TX_DMA_STOPPED_INT
When this bit is asserted, the TX DMA FSM is stopped.
0
R
0
TX_INT
When this bit is asserted, a frame transmission is completed.
8.9.4.4. Interrupt Enable Register(Default Value: 0x00000000)
Offset: 0x0C
Register Name: INT_EN
Bit
R/W
Default/Hex
Description
31:14
/
/
/
13
R/W
0
RX_EARLY_INT_EN
0: Disable early receive interrupt enable
1: Enable early receive interrupt enable
12
R/W
0
RX_OVERFLOW_INT_EN
0: Disable overflow interrupt
1: Enable overflow interrupt
11
R/W
0
RX_TIMEOUT_INT_EN
0: Disable receive timeout interrupt
1: Enable receive timeout interrupt
10
R/W
0
RX_DMA_STOPPED_INT_EN
0: Disable receive DMA FSM stopped interrupt
1: Enable receive DMA FSM stopped interrupt
9
R/W
0
RX_BUF_UA_INT_EN
0: Disable receive buffer unavailable interrupt
1: Enable receive buffer unavailable interrupt
8
R/W
0
RX_INT_EN
0: Disable receive interrupt
1: Enable receive interrupt
7:6
5
R/W
0
TX_EARLY_INT_EN
0: Disable early transmit interrupt
1: Enable early transmit interrupt
4
R/W
0
TX_UNDERFLOW_INT_EN
0: Disable underflow interrupt
1: Enable underflow interrupt
3
R/W
0
TX_TIMEOUT_INT_EN
0: Disable transmit timeout interrupt
confidential