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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 576
001: 128
010: 192
011: 256
Others: Reserved
7:2
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/
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1
R/W
0
TX_MD
0: Transmission starts after the number of data in TX DAM FIFO is greater
than TX_TH
1: Transmission starts after a full frame located in TX DMA FIFO
0
R/W
0
FLUSH_TX_FIFO
The functionality that flush the data in the TX FIFO.
0: Enable
1: Disable
8.9.4.7. Transmit Flow Control Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: TX_FLOW_CTL
Bit
R/W
Default/Hex
Description
31
R/W
0
TX_FLOW_CTL_STA
This bit indicates a pause frame transmission is in progress. When the
configuration of flow control is ready, set this bit to transmit a pause frame
in full-duplex mode or activate the backpressure function. After completion
of transmission, this bit will be cleared automatically. Before write register
TX_FLOW_CTRL, this bit must be read as 0.
30:22
/
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21:20
R/W
0
TX_PAUSE_FRM_SLOT
The threshold of the pause timer at which the input flow control signal is
checked for automatic retransmission of pause frame. The threshold values
should be always less than the PAUSE_TIME
19:4
R/W
0
PAUSE_TIME
The pause time field in the transmitted control frame.
3:2
/
/
/
1
R/W
0
ZQP_FRM_EN
When set, enable the functionality to generate Zero-Quanta Pause control
frame.
0
R/W
0
TX_FLOW_CTL_EN
When set, enable flow control operation to transmit pause frames in
full-duplex mode, or enable the back-pressure operation in half-duplex
mode.
0: Disable
1: Enable
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