Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 577
8.9.4.8. Transmit DMA Descriptor List Address Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: TX_DMA_LIST
Bit
R/W
Default/Hex
Description
31:0
R/W
0
TX_DESC_LIST
The base address of transmit descriptor list. It must be 32-bit aligned.
8.9.4.9. Receive Control 0 Register(Default Value: 0x00000000)
Offset: 0x24
Register Name: RX_CTL_0
Bit
R/W
Default/Hex
Description
31
R/W
0
RX_EN
Enable receiver
0: Disable receiver after current reception
1: Enable
30
R/W
0
RX_FRM_LEN_CTL
0: Allow to receive frames less than or equal to 2,048 bytes (10,240 if
JUMBO_FRM_EN is set) and cuts off any bytes received after that
1: Allow to receive frames of up to 16,384 bytes
29
R/W
0
JUMBO_FRM_EN
When set, allows Jumbo frames of 9,018 bytes without reporting a giant
frame error in the receive frame status.
28
R/W
0
STRIP_FCS
When set, strip the Pad/FCS field on received frames only when the length’s
field value is less than or equal to 1,500 bytes.
27
R/W
0
CHECK_CRC
When set, calculate CRC and check the IPv4 Header Checksum.
26:18
/
/
/
17
R/W
0
RX_PAUSE_FRM_MD
0: Only detect multicast pause frame specified in the 802.3x standard.
1: In addition to detect multicast pause frame specified in the 802.3x
standard, also detect unicast pause frame with address specified in MAC
Address 0 High Register and MAC address 0 Low Register.
16
R/W
0
RX_FLOW_CTL_EN
When set, enable the functionality that decode the received pause frame
and disable its transmitter for a specified time by pause frame.
15:0
/
/
/
8.9.4.10. Receive Control 1 Register(Default Value: 0x00000000)
Offset: 0x28
Register Name: RX_CTL_1
Bit
R/W
Default/Hex
Description
confidential