Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 579
frame has been written to RX DMA FIFO
0
R/W
0
FLUSH_RX_FRM
The functionality that flush the frames when receive descriptors/buffers is
unavailable
0: Enable
1: Disable
8.9.4.11. Receive DMA Descriptor List Address Register(Default Value: 0x00000000)
Offset: 0x34
Register Name: RX_DMA_LIST
Bit
R/W
Default/Hex
Description
31:0
R/W
0
RX_DESC_LIST
The base address of receive descriptor list. It must be 32-bit aligned.
8.9.4.12. Receive Frame Filter Register(Default Value: 0x00000000)
Offset: 0x38
Register Name: RX_FRM_FLT
Bit
R/W
Default/Hex
Description
31
R/W
0
DIS_ADDR_FILTER
0: Enable address filter
1: Disable address filter
30:18
/
/
/
17
R/W
0
DIS_BROADCAST
0: Receive all broadcast frames
1: Drop all broadcast frames
16
R/W
0
RX_ALL_MULTICAST
0: Filter multicast frame according to HASH_MULTICAST
1: Receive all multicast frames
15:14
/
/
13:12
R/W
0
CTL_FRM_FILTER
00, 01: Drop all control frames
10: Receive all control frames
11: Receive all control frames when pass the address filter
11:10
/
/
/
9
R/W
0
HASH_MULTICAST
0: Filter multicast frames by comparing the DA field with the values in DA
MAC address registers
1: Filter multicast frames according to the hash table
8
R/W
0
HASH_UNICAST
0: Filter unicast frames by comparing the DA field with the values in DA MAC
address registers
1: Filter unicast frames according to the hash table
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