Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 581
8.9.4.15. MII Command Register(Default Value: 0x00000000)
Offset: 0x48
Register Name: MII_CMD
Bit
R/W
Default/Hex
Description
31:23
/
/
/
22:20
R/W
0
MDC_DIV_RATIO_M
MDC clock divide ration(m). The source of MDC clock is AHB clock.
000: 16
001: 32
010: 64
011: 128
Others: Reserved
19:17
/
/
/
16:12
R/W
0
PHY_ADDR
Select a PHY device from 32 possible candidates.
11:9
/
/
/
8:4
R/W
0
PHY_REG_ADDR
Select register in the selected PHY device
3:2
/
/
/
1
R/W
0
MII_WR
0: Read register in selected PHY and return data in EMAC_GMII_DATA
1: Write register in selected PHY using data in EMAC_GMII_DATA
0
R/W
0
MII_BUSY
This bit indicates that a read or write operation is in progress. When prepared
the data and register address for a write operation or the register address for a
read operation, set this bit and start to access register in PHY.
When this bit is cleared automatically, the read or write operation is over and
the data in EMAC_GMII_DATA is valid for a read operation.
8.9.4.16. MII Data Register(Default Value: 0x00000000)
Offset: 0x4C
Register Name: MII_DATA
Bit
R/W
Default/Hex
Description
31:16
/
/
/
15:0
R/W
0
MII_DATA
The 16-bit data to be written to or read from the register in the selected PHY.
8.9.4.17. MAC Address 0 High Register(Default Value: 0x0000FFFF)
Offset: 0x50
Register Name: ADDR0_HIGH
Bit
R/W
Default/Hex
Description
31:16
/
/
/
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