Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 583
8.9.4.21. Transmit DMA Status Register(Default Value: 0x00000000)
Offset: 0xB0
Register Name: TX_DMA_STA
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2:0
R
0
TX_DMA_STA
The state of Transmit DMA FSM.
000: STOP: When reset or disable TX DMA;
001: RUN_FETCH_DESC: Fetching TX DMA descriptor;
010: RUN_WAIT_STA: Waiting for the status of TX frame;
011: RUN_TRANS_DATA: Passing frame from host memory to TX DMA FIFO;
111: RUN_CLOSE_DESC: Closing TX descriptor.
110: SUSPEND: TX descriptor unavailable or TX DMA FIFO underflow;
100, 101: Reserved;
8.9.4.22. Transmit DMA Current Descriptor Register(Default Value: 0x00000000)
Offset: 0xB4
Register Name: TX_DMA_CUR_DESC
Bit
R/W
Default/Hex
Description
31:0
R
0
The address of current transmit descriptor.
8.9.4.23. Transmit DMA Current Buffer Address Register(Default Value: 0x00000000)
Offset: 0xB8
Register Name: TX_DMA_CUR_BUF
Bit
R/W
Default/Hex
Description
31:0
R
0
The address of current transmit DMA buffer
8.9.4.24. Receive DMA Status Register(Default Value: 0x00000000)
Offset: 0xC0
Register Name: RX_DMA_STA
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2:0
R
0
RX_DMA_STA
The state of RX DMA FSM.
000: STOP: When reset or disable RX DMA;.
001: RUN_FETCH_DESC: Fetching RX DMA descriptor;
011: RUN_WAIT_FRM: Waiting for frame.
100: SUSPEND: RX descriptor unavailable;
101: RUN_CLOSE_DESC: Closing RX descriptor.
111: RUN_TRANS_DATA: Passing frame from host memory to RX DMA FIFO;
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