Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 584
010, 110: Reserved.
8.9.4.25. Receive DMA Current Descriptor Register(Default Value: 0x00000000)
Offset: 0xC4
Register Name: RX_DMA_CUR_DESC
Bit
R/W
Default/Hex
Description
31:0
R
0
The address of current receive descriptor
8.9.4.26. Receive DMA Current Buffer Address Register(Default Value: 0x00000000)
Offset: 0xC8
Register Name: RX_DMA_CUR_BUF
Bit
R/W
Default/Hex
Description
31:0
R
0
The address of current receive DMA buffer
8.9.4.27. RGMII Status Register(Default Value: 0x00000000)
Offset: 0xD0
Register Name: RGMII_STA
Bit
R/W
Default/Hex
Description
31:4
/
/
/
3
R
0
RGMII_LINK
The link status of RGMII interface
0: down
1: up
2:1
R
0
RGMII_LINK_SPD
The link speed of RGMII interface
00: 2.5 MHz
01: 25 MHz
10: 125 MHz
0
R
0
RGMII_LINK_MD
The link Mode of RGMII interface
0: Half-Duplex
1: Full-Duplex
8.9.5. EMAC RX/TX Descriptor
The EMAC’ internal DMA transfers data between host memory and internal RX/TX FIFO with a linked list of descriptors.
Each descriptor is consisted of four words, and contains some necessary information to transfer TX and RX frames.
The descriptor list structure is shown in figure 8-20. The address of each descriptor must be 32-bit aligned.
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