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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 585
4th: Next Desc
1st: Status
2nd: Buffer Size
2rd: Buffer Addr
1st Desc 2nd Desc 3rd Desc N-th Desc
…
Desc List Base Addr
4th: Next Desc
1st: Status
2nd: Buffer Size
2rd: Buffer Addr
4th: Next Desc
1st: Status
2nd: Buffer Size
2rd: Buffer Addr
4th: Next Desc
1st: Status
2nd: Buffer Size
2rd: Buffer Addr
Figure 8-20. EMAC RX/TX Descriptor List
8.9.5.1. Transmit Descriptor
1st Word of Transmit Descriptor
Bits
Description
31
TX_DESC_CTL
When set, current descriptor can be used by DMA. This bit is cleared by DMA when the whole frame is
transmitted or all data in current descriptor’s buffer are transmitted.
30:17
Reserved
16
TX_HEADER_ERR
When set, the checksum of transmitted frame’s header is wrong.
15
Reserved
14
TX_LENGHT_ERR
When set, the length of transmitted frame is wrong.
13
Reserved
12
TX_PAYLOAD_ERR
When set, the checksum of transmitted frame’s payload is wrong.
11
Reserved
10
TX_CRS_ERR
When set, carrier is lost during transmission.
9
TX_COL_ERR_0
When set, the frame is aborted because of collision after contention period.
8
TX_COL_ERR_1
When set, the frame is aborted because of too many collisions.
7
Reserved.
6:3
TX_COL_CNT
The number of collisions before transmission.
2
TX_DEFER_ERR
When set, the frame is aborted because of too much deferral.
1
TX_UNDERFLOW_ERR
When set, the frame is aborted because of TX FIFO underflow error.
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