Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 586
0
TX_DEFER
When set in Half-Duplex mode, the EMAC defers the frame transmission.
2nd Word of Transmit Descriptor
Bits
Description
31
TX_INT_CTL
When set and the current frame have been transmitted, the TX_INT in Interrupt Status Register will be
set.
30
LAST_DESC
When set, current descriptor is the last one for current frame.
29
FIR_DESC
When set, current descriptor is the first one for current frame.
28:27
CHECKSUM_CTL
These bits control to insert checksums in transmit frame.
26
CRC_CTL
When set, CRC field is not transmitted.
25:11
Reserved
10:0
BUF_SIZE
The size of buffer specified by current descriptor.
3rd Word of Transmit Descriptor
Bits
Description
31:0
BUF_ADDR
The address of buffer specified by current descriptor.
4th Word of Transmit Descriptor
Bits
Description
31:0
NEXT_DESC_ADDR
The address of next descriptor. It must be 32-bit aligned.
8.9.5.2. Receive Descriptor
1st Word of Receive Descriptor
Bits
Description
31
RX_DESC_CTL
When set, current descriptor can be used by DMA. This bit is cleared by DMA when complete frame is
received or current descriptor’s buffer is full.
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