Owners manual

Overview

2.1.4.8. Crypto Engine(CE)

 Support symmetrical algorithm: AES, DES, TDES

 Support hash algorithm:SHA-1/SHA-224/SHA-256,SHA384,SHA512,MD5,HMAC-SHA1

 Support 160-bits hardware PRNG with 175-bits seed

 Support 256-bits TRNG

 Support ECB,CBC, CTR, CTS,OFB,CFB,CBC-MAC modes for AES

 Support ECB, CBC, CTR,CBC-MAC modes for DES

 Support ECB, CBC, CTR modes for TDES

 128-bits, 192-bits and 256-bits key size for AES

 Embedded special DMA to do data transfer

2.1.4.9. Security ID

 Support 2K-bits EFUSE for chip ID and security application

2.1.4.10. CPU Configuration

 Support power clamp

 Flexible CPU configuration

2.1.4.11. Power Management

 Support DVFS for CPU frequency and voltage adjustment

 Flexible clock gate and module reset

 Dynamic frequency adjustment for external DRAM

 Multiple power domains

2.1.5. Display Subsystem

2.1.5.1. DE2.0

 Output size up to 4096x4096

 Support four alpha blending channel for main display, two channel for aux display

 Support four overlay layers in each channel, and has a independent scaler

 Support potter-duff compatible blending operation

 Support input format YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555 and

RGB565

 Support Frame Packing/Top-and-Bottom/Side-by-side Full/Side-by-Side Half 3D format data

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