Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 592
8.10.3. Transport Stream Controller Register List
Module Name
Base Address
TSC
0x01C06000
TSG OFFSET
0x00000040
TSF0 OFFSET
0x00000080
TSF1 OFFSET
0x00000100
TSD OFFSET
0x00000180
Register Name
Offset
Description
TSC_CTLR
TSC + 0x00
TSC Control Register
TSC_STAR
TSC + 0x04
TSC Status Register
TSC_PCTLR
TSC + 0x10
TSC Port Control Register
TSC_PPARR
TSC + 0x14
TSC Port Parameter Register
TSC_TSFMUXR
TSC + 0x20
TSC TSF Input Multiplex Control Register
TSC_OUTMUXR
TSC + 0x28
TSC Port Output Multiplex Control Register
TSG_CTLR
TSG + 0x00
TSG Control Register
TSG_PPR
TSG + 0x04
TSG Packet Parameter Register
TSG_STAR
TSG + 0x08
TSG Status Register
TSG_CCR
TSG + 0x0c
TSG Clock Control Register
TSG_BBAR
TSG + 0x10
TSG Buffer Base Address Register
TSG_BSZR
TSG + 0x14
TSG Buffer Size Register
TSG_BPR
TSG + 0x18
TSG Buffer Pointer Register
TSF_CTLR
TSF + 0x00
TSF Control Register
TSF_PPR
TSF + 0x04
TSF Packet Parameter Register
TSF_STAR
TSF + 0x08
TSF Status Register
TSF_DIER
TSF + 0x10
TSF DMA Interrupt Enable Register
TSF_OIER
TSF + 0x14
TSF Overlap Interrupt Enable Register
TSF_DISR
TSF + 0x18
TSF DMA Interrupt Status Register
TSF_OISR
TSF + 0x1c
TSF Overlap Interrupt Status Register
TSF_PCRCR
TSF + 0x20
TSF PCR Control Register
TSF_PCRDR
TSF + 0x24
TSF PCR Data Register
TSF_CENR
TSF + 0x30
TSF Channel Enable Register
TSF_CPER
TSF + 0x34
TSF Channel PES Enable Register
TSF_CDER
TSF + 0x38
TSF Channel Descramble Enable Register
TSF_CINDR
TSF + 0x3c
TSF Channel Index Register
TSF_CCTLR
TSF + 0x40
TSF Channel Control Register
TSF_CSTAR
TSF + 0x44
TSF Channel Status Register
TSF_CCWIR
TSF + 0x48
TSF Channel CW Index Register
TSF_CPIDR
TSF + 0x4c
TSF Channel PID Register
TSF_CBBAR
TSF + 0x50
TSF Channel Buffer Base Address Register
TSF_CBSZR
TSF + 0x54
TSF Channel Buffer Size Register
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