Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 594
TS Input Port0 Parameters
Bit
Definition
7:5
Reserved
4
SSI data order
0: MSB first for one byte data
1: LSB first for one byte data
3
CLOCK signal polarity
0 : Rise edge capturing
1: Fall edge capturing
2
ERROR signal polarity
0: High level active
1: Low level active
1
DVALID signal polarity
0: High level active
1: Low level active
0
PSYNC signal polarity
0: High level active
1: Low level active
8.10.4.5. TSC TSF Input Multiplex Control Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: TSC_TSFMUXR
Bit
R/W
Default/Hex
Description
31:4
/
/
/
3:0
R/W
0x0
TSF0InputMuxCtrl
TSF0 Input Multiplex Control
0x0 –Data from TSG
0x1 –Data from TS IN Port0
Others – Reserved
8.10.4.6. TSC Port Output Multiplex Control Register(Default Value: 0x00000000)
Offset: 0x28
Register Name: TSC_TSFMUXR
Bit
R/W
Default/Hex
Description
31:0
/
/
/
8.10.4.7. TSC Port Output Multiplex Control Register(Default Value: 0x00000000)
Offset: TSG+0x00
Register Name: TSC_TSFMUXR
Bit
R/W
Default/Hex
Description
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