Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 595
31:26
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25:24
R
0
TSGSts
Status for TS Generator
0: IDLE state
1: Running state
2: PAUSE state
Others: Reserved
23:10
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9
R/W
0
TSGLBufMode
Loop Buffer Mode
When set to ‘1’, the TSG external buffer is in loop mode.
8
R/W
0
TSGSyncByteChkEn
Sync Byte Check Enable
Enable/ Disable check SYNC byte fro receiving new packet
0: Disable
1: Enable
If enable check SYNC byte and an error SYNC byte is receiver, TS Generator
would come into PAUSE state. If the correspond interrupt is enable, the
interrupt would happen.
7:3
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2
R/W
0
TSGPauseBit
Pause Bit for TS Generator
Write ‘1’ to pause TS Generator. TS Generator would stop fetch new data
from DRAM. After finishing this operation, this bit will clear to zero by
hardware. In PAUSE state, write ‘1’ to resume this state.
1
R/W
0
TSGStopBit
Stop Bit for TS Generator
Write ‘1’ to stop TS Generator. TS Generator would stop fetch new data
from DRAM. The data already in its FIFO should be sent to TS filter. After
finishing this operation, this bit will clear to zero by hardware.
0
R/W
0
TSGStartBit
Start Bit for TS Generator
Write ‘1’ to start TS Generator. TS Generator would fetch data from DRAM
and generate SPI stream to TS filter. This bit will clear to zero by hardware
after TS Generator is running.
8.10.4.8. TSG Packet Parameter Register(Default Value: 0x00470000)
Offset: TSG+0x04
Register Name: TSG_PPR
Bit
R/W
Default/Hex
Description
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23:16
R/W
0x47
SyncByteVal
Sync Byte Value
This is the value of sync byte used in the TS Packet.
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