Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 596
15:8
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/
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7
R/W
0
SyncBytePos
Sync Byte Position
0: the 1st byte position
1: the 5th byte position
Notes: This bit is only used for 192 bytes packet size.
6:2
/
/
/
1:0
R/W
0
PktSize
Packet Size
Byte Size for one TS packet
0: 188 bytes
Others: Reserved
8.10.4.9. TSG Interrupt Enable and Status Register(Default Value: 0x00000000)
Offset: TSG+0x08
Register Name: TSG_IESR
Bit
R/W
Default/Hex
Description
31:20
/
/
/
19
R/W
0
TSGEndIE
TS Generator (TSG) End Interrupt Enable
0: Disable
1: Enable
If set this bit, the interrupt would assert to CPU when all data in external
DRAM are sent to TS PID filter.
18
R/W
0
TSGFFIE
TS Generator (TSG) Full Finish Interrupt Enable
0: Disable
1: Enable
17
R/W
0
TSGHFIE
TS Generator (TSG) Half Finish Interrupt Enable
0: Disable
1: Enable
16
R/W
0
TSGErrSyncByteIE
TS Generator (TSG) Error Sync Byte Interrupt Enable
0: Disable
1: Enable
15:4
/
/
/
3
R/W
0
TSGEndSts
TS Generator (TSG) End Status
Write ‘1’ to clear.
2
R/W
0
TSGFFSts
TS Generator (TSG) Full Finish Status
Write ‘1’ to clear.
1
R/W
0
TSGHFSts
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