Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 597
TS Generator (TSG) Half Finish Status
Write ‘1’ to clear.
0
R/W
0
TSGErrSyncByteSts
TS Generator (TSG) Error Sync Byte Status
Write ‘1’ to clear.
8.10.4.10. TSG Clock Control Register(Default Value: 0x00000000)
Offset: TSG+0x0C
Register Name: TSG_CCR
Bit
R/W
Default/Hex
Description
31:16
R/W
0x0
TSGCDF_N
TSG Clock Divide Factor (N)
The Numerator part of TSG Clock Divisor Factor.
15:0
R/W
0x0
TSGCDF_D
TSG Clock Divide Factor (D)
The Denominator part of TSG Clock Divisor Factor.
Frequency of output clock:
Fo = (Fi*(N+1))/(8*(D+1)).
Fi is the input special clock of TSC, and D must not less than N.
8.10.4.11. TSG Buffer Base Address Register(Default Value: 0x00000000)
Offset: TSG+0x10
Register Name: TSG_BBAR
Bit
R/W
Default/Hex
Description
31:28
/
/
/
27:0
RW
0x0
TSGBufBase
Buffer Base Address
This value is a start address of TSG buffer.
Note: This value should be 4-word (16Bytes) align, and the lowest 4-bit of
this value should be zero.
8.10.4.12. TSG Buffer Size Register(Default Value: 0x00000000)
Offset: TSG+0x14
Register Name: TSG_BSZR
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23:0
R/W
0
TSGBufSize
Data Buffer Size for TS Generator
It is in byte unit.
The size should be 4-word (16Bytes) align, and the lowest 4 bits should be
zero.
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