Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 600
1
R
0
TSFCOIS
TS PID Filter (TSF) Channel Overlap Status
It is global status for 16 channel. It would clear to zero after all channels
status bits are clear.
0
R
0
TSFCDIS
TS PID Filter (TSF) Channel DMA status
It is global status for 16 channel. It would clear to zero after all channels
status bits are clear.
8.10.4.17. TSF DMA Interrupt Enable Register(Default Value: 0x00000000)
Offset: TSF+0x10
Register Name: TSF_DIER
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
DMAIE
DMA Interrupt Enable
DMA interrupt enable bits for channel 0~31.
8.10.4.18. TSF Overlap Interrupt Enable Register(Default Value: 0x00000000)
Offset: TSF+0x14
Register Name: TSF_OIER
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
OLPIE
Overlap Interrupt Enable
Overlap interrupt enable bits for channel 0~31.
8.10.4.19. TSF DMA Interrupt Status Register(Default Value: 0x00000000)
Offset: TSF+0x18
Register Name: TSF_DISR
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
DMAIS
DMA Interrupt Status
DMA interrupt Status bits for channel 0~31.
Set by hardware, and can be cleared by software writing ‘1’.
When both these bits and the corresponding DMA Interrupt Enable bits
set, the TSF interrupt will generate.
8.10.4.20. TSF Overlap Interrupt Status Register(Default Value: 0x00000000)
Offset: TSF+0x1C
Register Name: TSF_OISR
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