Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 601
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
OLPIS
Overlap Interrupt Status
Overlap interrupt Status bits for channel 0~31.
Set by hardware, and can be cleared by software writing ‘1’.
When both these bits and the corresponding Overlap Interrupt Enable bits
set, the TSF interrupt will generate.
8.10.4.21. TSF PCR Control Register(Default Value: 0x00000000)
Offset: TSF+0x20
Register Name: TSF_PCRCR
Bit
R/W
Default/Hex
Description
31:17
/
/
/
16
R/W
0
PCRDE
PCR Detecting Enable
0: Disable
1: Enable
15:13
/
/
/
12:8
R/W
0
PCRCIND
Channel Index m for Detecting PCR packet (m from 0 to 31)
7:1
/
/
/
0
R
0
PCRLSB
PCR Contest LSB 1 bit
PCR[0]
8.10.4.22. TSF PCR Data Register(Default Value: 0x00000000)
Offset: TSF+0x24
Register Name: TSF_PCRDR
Bit
R/W
Default/Hex
Description
31:0
R
0
PCRMSB
PCR Data High 32 bits
PCR[33:1]
8.10.4.23. TSF Channel Enable Register(Default Value: 0x00000000)
Offset: TSF+0x30
Register Name: TSF_CENR
Bit
R/W
Default/Hex
Description
31:0
R/W
0
FilterEn
Filter Enable for Channel 0~31
0: Disable
1: Enable
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