Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 602
From Disable to Enable, internal status of the corresponding filter channel
will be reset.
8.10.4.24. TSF PES Enable Register(Default Value: 0x00000000)
Offset: TSF+0x34
Register Name: TSF_CPER
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
PESEn
PES Packet Enable for Channel 0~31
0: Disable
1: Enable
These bits should not be changed during the corresponding channel
enable.
8.10.4.25. TSF Channel Descramble Enable Register(Default Value: 0x00000000)
Offset: TSF+0x38
Register Name: TSF_CDER
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
DescEn
Descramble Enable for Channel 0~31
0: Disable
1: Enable
These bits should not be changed during the corresponding channel
enable.
8.10.4.26. TSF Channel Index Register(Default Value: 0x00000000)
Offset: TSF+0x3C
Register Name: TSF_CINDR
Bit
R/W
Default/Hex
Description
31:5
/
/
/
4:0
R/W
0x0
CHIND
Channel Index
This value is the channel index for channel private registers access.
Range is from 0x00 to 0x1f.
Address range of channel private registers is 0x40~0x7f.
8.10.4.27. TSF Channel Control Register(Default Value: 0x00000000)
Offset: TSF+0x40
Register Name: TSF_CCTLR
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