Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 603
Bit
R/W
Default/Hex
Description
31:0
/
/
/
8.10.4.28. TSF Channel Status Register(Default Value: 0x00000000)
Offset: TSF+0x44
Register Name: TSF_CSTAR
Bit
R/W
Default/Hex
Description
31:0
/
/
/
8.10.4.29. TSF Channel CW Index Register(Default Value: 0x00000000)
Offset: TSF+0x48
Register Name: TSF_CCWIR
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2:0
R/W
0x0
CWIND
Related Control Word Index
Index to the control word used by this channel when Descramble Enable of
this channel enable.
This value is useless when the corresponding Descramble Enable is ‘0’.
8.10.4.30. TSF Channel PID Register(Default Value: 0x1FFF0000)
Offset: TSF+0x4C
Register Name: TSF_CPIDR
Bit
R/W
Default/Hex
Description
31:16
R/W
0x1fff
PIDMSK
Filter PID Mask for Channel
15:0
R/W
0x0
PIDVAL
Filter PID value for Channel
8.10.4.31. TSF Channel Buffer Base Address Register(Default Value: 0x00000000)
Offset: TSF+0x50
Register Name: TSF_CBBAR
Bit
R/W
Default/Hex
Description
31:28
/
/
/
27:0
R/W
0
TSFBufBAddr
Data Buffer Base Address for Channel
It is 4-word (16Bytes) align address. The LSB four bits should be zero.
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