Owners manual

Appendix
H3 Datasheet(Revision 1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 613
Appendix
Pin Map
The following figure shows the pin maps of the 347-pin FBGA package of H3 processor.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A
JTAG-
SEL0
EPHY_
LINK_LE
D
EPHY_
TXN
EPHY_
RXN
USB_
DP0
USB_
DP2
USB_
DM2
PE1
PE11
PA20
PA21
PC7
PC5
PF1
PD4
GND
A
B
PG13
JTAG-
SEL1
EPHY_
TXP
EPHY_
RXP
USB_
DM0
USB_
DP1
USB_
DM1
USB_
DP3
USB_
DM3
PE0
PE2
PE12
PA18
PA19
PC3
PC2
PC12
PC8
PC13
PD2
PD6
B
C
PG5
PG4
PG8
PE15
PE14
PE13
PE7
PE4
PE3
PE8
PE9
PA12
PA17
PC0
PC1
PC9
PC11
PC15
PF5
PD0
C
D
PG12
PG11
PG7
PA1
PA2
PA7
PE6
PA0
PA9
PA16
PC10
PF0
PF2
D
E
HTXCN
PG9
PE10
PE5
PA10
PA3
PA6
PA13
PC6
PD7
PD12
PD8
PF4
E
F
HTX0N
HTXCP
PG3
PA4
EPHY_
RTX
EPHY_
SPD_LE
D
EPHY_
VDD
TVOUT
PA11
PA8
PA15
PC4
PC14
PF3
PD5
PD11
PD9
F
G
HTX0P
HTX1N
PG6
HCEC
EPHY_
VCC
GND
V33_TV
VDD_
EFUSE
VCC_
USB
PA14
VCC_IO
VCC_IO
VCC_IO
PF6
SDQM1
G
H
HTX1P
HSCL
PG2
PA5
VCC_PG
GND_TV
VDD_
SYS
VDD_EF
USEBP
GND
VCC_IO
VCC_IO
GND
PC16
PD1
PD3
PD10
SDQ9
SDQ10
H
J
HTX2P
HTX2N
PG0
HVCC
VDD_
CPUS
VDD_
CPUS
GND
VDD_
SYS
VDD_
SYS
VDD_
SYS
GND
VCC_IO
VCC_PD
GND
SDQ8
SDQS1B
SDQ11
J
K
X24MO
UT
X24MIN
HSDA
NC
VCC_
RTC
GND
GND
GND
VDD_
SYS
VDD_
SYS
VDD_
SYS
GND
GND
GND
GND
PD13
PD15
SDQS1
K
L
PG1
PLLTEST
GND
GND
VDD_
SYS
VDD_
SYS
VDD_
SYS
VDD_
SYS
VDD_
SYS
GND
VCC-
DRAM
PD14
PD16
PD17
SDQ12
SDQ13
L
M
PL1
HHPD
PG10
RTC_VIO
HGND
PL9
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC-
DRAM
SDQ15
SDQM0
SDQ14
M
N
PL0
PL4
VCC_PLL
GND
VDD_
CPUX
GND
GND
GND
GND
GND
GND
GND
VCC-
DRAM
SA14
SA11
SDQ0
N
P
PL2
X32KFO
UT
VDD_
CPUX
VDD_
CPUX
VDD_
CPUX
VDD_
CPUX
GND
GND
GND
GND
GND
GND
VCC-
DRAM
VCC-
DRAM
SA10
SDQ2
SDQ1
P
R
PL3
PL5
VDD_
CPUX
VDD_
CPUX
VDD_
CPUX
GND
GND
GND
GND
GND
GND
VCC-
DRAM
SA15
SA12
SDQ4
SDQS0
SDQS0B
R
T
PL8
PL7
PL6
TEST
VDD_
CPUX
VDD_
CPUX
VDD_
CPUX
GND-
CPUFB
VDD_
CPUFB
GND
VCC-
DRAM
VCC-
DRAM
VCC-
DRAM
VCC-
DRAM
SVREF
SA0
SBA1
SDQ5
T
U
PL11
AGND
X32KOU
T
VDD_
CPUX
VDD_
CPUX
VCC-
DRAM
SCAS
SRST
SA1
SDQ6
SDQ7
SDQ3
U
V
LINEINL
PL10
AVCC
VRP
X32KIN
RESET
SZQ
SODT1
SA13
SRAS
SA7
SBA2
SA2
SA3
SA4
V
W
LINEINR
MICIN1P
MBIAS
VRA2
UBOOT
SDQ28
SODT0
SDQ24
SWE
SDQ19
SBA0
SA8
SCS0
SCS1
W
Y
MICIN1
N
MICIN2P
LINEOU
TR
VRA1
SDQ31
SDQ30
SDQS3B
SDQ27
SDQ26
SDQ23
SDQ22
SDQ20
SDQS2B
SDQ18
SDQ16
SA9
SA5
SA6
SCKE1
Y
A
A
GND
MICIN2
N
LINEOU
TL
KEYADC
NMI
SDQ29
SDQS3
SDQ25
SDQM3
SDQ21
SDQS2
SDQ17
SDQM2
SCK
SCKB
SCKE0
AA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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