Owners manual

H3
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 7
4.3.5.4. PLL_VE Control Register (Default Value: 0x03006207)................................................................ 95
4.3.5.5. PLL_DDR Control Register (Default Value: 0x00001000) ............................................................. 96
4.3.5.6. PLL_PERIPH0 Control Register (Default Value: 0x00041811) ...................................................... 97
4.3.5.7. PLL_GPU Control Register (Default Value: 0x03006207) ............................................................. 98
4.3.5.8. PLL_PERIPH1 Control Register (Default Value: 0x00041811) ...................................................... 99
4.3.5.9. PLL_DE Control Register (Default Value: 0x03006207) ............................................................. 100
4.3.5.10. CPUX/AXI Configuration Register (Default Value: 0x00010000) ............................................. 101
4.3.5.11. AHB1/APB1 Configuration Register (Default Value: 0x00001010)........................................... 102
4.3.5.12. APB2 Configuration Register (Default Value: 0x01000000) .................................................... 102
4.3.5.13. AHB2 Configuration Register (Default Value: 0x00000000) .................................................... 103
4.3.5.14. Bus Clock Gating Register0 (Default Value: 0x00000000) ....................................................... 103
4.3.5.15. Bus Clock Gating Register1 (Default Value: 0x00000000) ....................................................... 105
4.3.5.16. Bus Clock Gating Register2 (Default Value: 0x00000000) ....................................................... 106
4.3.5.17. Bus Clock Gating Register3 (Default Value: 0x00000000) ....................................................... 107
4.3.5.18. Bus Clock Gating Register4 (Default Value: 0x00000000) ....................................................... 108
4.3.5.19. THS Clock Register (Default Value: 0x00000000) .................................................................... 109
4.3.5.20. NAND Clock Register (Default Value: 0x00000000) ................................................................ 109
4.3.5.21. SDMMC0 Clock Register (Default Value: 0x00000000) ........................................................... 110
4.3.5.22. SDMMC1 Clock Register (Default Value: 0x00000000) ........................................................... 111
4.3.5.23. SDMMC2 Clock Register (Default Value: 0x00000000) ........................................................... 112
4.3.5.24. TS Clock Register (Default Value: 0x00000000) ....................................................................... 113
4.3.5.25. CE Clock Register (Default Value: 0x00000000) ...................................................................... 113
4.3.5.26. SPI0 Clock Register (Default Value: 0x00000000) ................................................................... 114
4.3.5.27. SPI1 Clock Register (Default Value: 0x00000000) ................................................................... 114
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