Owners manual

Pin Description
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 78
3.3. Detailed Pin/Signal Description
Table 3-3 shows the detailed function description of every pin/signal based on the different interface.
Table 3-3. Detailed Pin/Signal Description
Pin/Signal Name
Description
Type
DRAM
SDQ[31:0]
DRAM bidirectional data line to the memory device
I/O
SDQS[3:0]
DRAM active-high bidirectional data strobes to the memory device
I/O
SDQSB[3:0]
DRAM active-low bidirectional data strobes to the memory device
I/O
SDQM[3:0]
DRAM data mask signal to the memory device
O
SCK
DRAM active-high clock signal to the memory device
O
SCKB
DRAM active-low clock signal to the memory device
O
SCKE[1:0]
DRAM clock enable signal to the memory device for two chip select
O
SA[15:0]
DRAM address signal to the memory device
O
SWE
DRAM write enable strobe to the memory device
O
SCAS
DRAM column address strobe to the memory device
O
SRAS
DRAM row address strobe to the memory device
O
SCS[1:0]
DRAM chip select signal to the memory device
O
SBA[2:0]
DRAM bank address signal to the memory device
O
SODT[1:0]
DRAM On-Die Termination output signal for two chip select
O
SRST
DRAM reset signal to the memory device
O
SZQ
DRAM ZQ Calibration
A
SVREF
DRAM Reference Input
P
VCC-DRAM
DRAM Power Supply
P
System
UBOOT
UBOOT Signal
I
TEST
TEST Signal
I
NMI
Non-Maskable Interrupt
I
RESET
RESET Signal
I
X32KFOUT
Clock Output Of 32768Hz LOSC
OD
X24MIN
Clock Input Of 24MHz Crystal
AI
X24MOUT
Clock Output Of 24MHz Crystal
AO
X32KIN
Clock Input Of 32KHz Crystal
AI
X32KOUT
Clock Output Of 32KHz Crystal
AO
VCC_RTC
RTC Power Supply
P
REXT
External Reference Register
AI
RTC-VIO
Internal LDO Output Bypass
P
HDMI
HTX0P
HDMI positive TMDS differential line driver data0 output
AO
HTX0N
HDMI negative TMDS differential line driver data0 output
AO
HTX1P
HDMI positive TMDS differential line driver data1 output
AO
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