Owners manual

H3
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 8
4.3.5.28. I2S/PCM 0 Clock Register (Default Value: 0x00000000) ......................................................... 115
4.3.5.29. I2S/PCM 1 Clock Register (Default Value: 0x00000000) ......................................................... 116
4.3.5.30. I2S/PCM 2 Clock Register (Default Value: 0x00000000) ......................................................... 116
4.3.5.31. OWA Clock Register (Default Value: 0x00000000) .................................................................. 116
4.3.5.32. USBPHY Configuration Register (Default Value: 0x00000000) ................................................ 117
4.3.5.33. DRAM Configuration Register (Default Value: 0x00000000) ................................................... 118
4.3.5.34. MBUS Reset Register (Default Value: 0x80000000) ................................................................ 119
4.3.5.35. DRAM Clock Gating Register (Default Value: 0x00000000)..................................................... 119
4.3.5.36. DE Clock Gating Register (Default Value: 0x00000000) .......................................................... 119
4.3.5.37. TCON0 Clock Register (Default Value: 0x00000000) ............................................................... 120
4.3.5.38. TVE Clock Register (Default Value: 0x00000000) .................................................................... 120
4.3.5.39. DEINTERLACE Clock Register (Default Value: 0x00000000) .................................................... 121
4.3.5.40. CSI_MISC Clock Register (Default Value: 0x00000000) ........................................................... 121
4.3.5.41. CSI Clock Register (Default Value: 0x00000000) ..................................................................... 121
4.3.5.42. VE Clock Register (Default Value: 0x00000000) ...................................................................... 122
4.3.5.43. AC Digital Clock Register (Default Value: 0x00000000) ........................................................... 123
4.3.5.44. AVS Clock Register (Default Value: 0x00000000) .................................................................... 123
4.3.5.45. HDMI Clock Register (Default Value: 0x00000000) ................................................................. 123
4.3.5.46. HDMI Slow Clock Register (Default Value: 0x00000000) ........................................................ 124
4.3.5.47. MBUS Clock Register (Default Value: 0x00000000) ................................................................ 124
4.3.5.48. GPU Clock Register (Default Value: 0x00000000) ................................................................... 124
4.3.5.49. PLL Stable Time Register0 (Default Value: 0x000000FF) ......................................................... 125
4.3.5.50. PLL Stable Time Register1 (Default Value: 0x000000FF) ......................................................... 125
4.3.5.51. PLL_CPUX Bias Register (Default Value: 0x08100200) ............................................................ 125
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