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System
H3 Datasheet(Revision1.2) Copyrigh 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 87
4.3. CCU
4.3.1. Overview
The CCU controls the PLLs configuration and most of the clock generation, division, distribution, synchronization and
gating. CCU input signals include the external clock for the reference frequency (24MHz). The outputs from CCU are
mostly clocks to other blocks in the system.
The CCU includes the following features:
9 PLLs, independent PLL for CPUX
Bus Source and Divisions
PLLs Bias Control
PLLs Tunning Control
PLLs Pattern Control
Configuring Modules Clock
Bus Clock Gating
Bus Software Reset
4.3.2. Functionalities Description
4.3.2.1. System Bus
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