Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 89
4.3.2.2. Bus clock tree
MUX
CPUX
INOSC / 512
X
PERIPH_ PLL
MUX
(1~4)
AHB1
APB_ CLK_ RATIO
(1/2/4/8)
APB1
MUX
CLK_PRE_DIV CLK_RATIO
(1~32)
APB2
PLL_CPUX
AXI
AXI_ CLK_ DIV_ RATIO
24M Hz
L2 Cache
/1
System
ATB / APB
ATB_ APB_CLK_DIV
(1/ 2/ 4)
AHB_CLK_ RATIO
(1/2/3/4)
AHB_PRE_DIV
(1~4)
(1/2/4/8)
Figure 4-2. Bus Clock Tree
4.3.3. Typical Applications
 Clock output of PLL_CPUX is used only for CPUX, and the frequency factor can be dynamically modified for DVFS;
 Clock output of PLL_AUDIO can be used for I2S/PCM, AC DIGITAL, OWA etc, and dynamic frequency scaling is not
supported;
 Clock output of PLL_PERIPH0 can be used for MBUS/AHB1/AHB2/APB1/APB2 and NAND/MMC/Crypto Engine /SPI
/CSI/ DE /DEINTERLACE etc, and dynamic frequency scaling is not supported;
 Clock output of PLL_PERIPH1 can be used for NAND/MMC/SPI/CSI/TVE/DEINTERLACE etc, and dynamic frequency
scaling is not supported;
 Clock output of PLL_VE can be used for VE , and dynamic frequency scaling is not supported;
 Clock output of PLL_DDR can be used for MBUS and DRAM, and dynamic frequency scaling is not supported;
 Clock output of PLL_VIDEO0 can be used for DE, TCON ,HDMI and CSI, and dynamic frequency scaling is not
supported;
 Clock output of PLL_DE can be used for DE,TCON and TVE, and dynamic frequency scaling is not supported;
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