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System

 Clock output of PLL_HSIC can be used for CCI-400 and USBPHY, and dynamic frequency scaling is not supported;

 Clock output of PLL_GPU can be used for GPU, and dynamic frequency scaling is not supported;

4.3.4. Register List

Module Name

Base Address

CCU

0x01C20000

Offset

Description

PLL_CPUX_CTRL_REG

0x0000

PLL_CPUX Control Register

PLL_AUDIO_CTRL_REG

0x0008

PLL_AUDIO Control Register

PLL_VIDEO_CTRL_REG

0x0010

PLL_VIDEO Control Register

PLL_VE_CTRL_REG

0x0018

PLL_VE Control Register

PLL_DDR_CTRL_REG

0x0020

PLL_DDR Control Register

PLL_PERIPH0_CTRL_REG

0x0028

PLL_PERIPH0 Control Register

PLL_GPU_CTRL_REG

0x0038

PLL_GPU Control Register

PLL_PERIPH1_CTRL_REG

0x0044

PLL_PERIPH1_CTRL_REG

PLL_DE_CTRL_REG

0x0048

PLL_DE Control Register

CPUX_AXI_CFG_REG

0x0050

CPUX/AXI Configuration Register

AHB1_APB1_CFG_REG

0x0054

AHB1/APB1 Configuration Register

APB2 _CFG_REG

0x0058

APB2 Configuration Register

AHB2_CFG_REG

0x005C

AHB2 Configuration Register

BUS_CLK_GATING_REG0

0x0060

Bus Clock Gating Register 0

BUS_CLK_GATING_REG1

0x0064

Bus Clock Gating Register 1

BUS_CLK_GATING_REG2

0x0068

Bus Clock Gating Register 2

BUS_CLK_GATING_REG3

0x006C

Bus Clock Gating Register 3

BUS_CLK_GATING_REG4

0x0070

Bus Clock Gating Register4

THS_CLK_REG

0x0074

THS Clock Register

NAND_CLK_REG

0x0080

NAND Clock Register

SDMMC0_CLK_REG

0x0088

SDMMC0 Clock Register

SDMMC1_CLK_REG

0x008C

SDMMC1 Clock Register

SDMMC2_CLK_REG

0x0090

SDMMC2 Clock Register

CE_CLK_REG

0x009C

CE Clock Register

SPI0_CLK_REG

0x00A0

SPI0 Clock Register

SPI1_CLK_REG

0x00A4

SPI1 Clock Register

I2S/PCM0_CLK_REG

0x00B0

I2S/PCM0 Clock Register

I2S/PCM1_CLK_REG

0x00B4

I2S/PCM1 Clock Register

I2S/PCM2_CLK_REG

0x00B8

I2S/PCM2 Clock Register

OWA_CLK_REG

0x00C0

OWA Clock Register

USBPHY_CFG_REG

0x00CC

USBPHY Configuration Register

DRAM_CFG_REG

0x00F4

DRAM Configuration Register

MBUS_RST_REG

0x00FC

MBUS Reset Register

DRAM_CLK_GATING_REG

0x0100

DRAM Clock Gating Register

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