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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 92
4.3.5. Register Description
4.3.5.1. PLL_CPUX Control Register (Default Value: 0x00001000)
Offset: 0x0000
Register Name: PLL_CPUX_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
PLL_ENABLE.
0: Disable
1: Enable
The PLL Output= (24MHz*N*K)/(M*P).
The PLL output is for the CPUX Clock.
Note: The PLL output clock must be in the range of 200MHz~2.6GHz.
Its default is 408MHz.
30:29
/
/
/
28
R
0x0
LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
27:25
/
/
/
24
R/W
0x0
CPUX_SDM_EN.
0: Disable
1: Enable
23:18
/
/
/
17:16
R/W
0x0
PLL_OUT_EXT_DIVP
PLL Output external divider P
00: /1
01: /2
10: /4
11: /
Note:The P factor only use in the condition that PLL output less than 288
MHz.
15:13
/
/
/
12:8
R/W
0x10
PLL_FACTOR_N
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3
……
Factor=31, N=32
7:6
/
/
/
5:4
R/W
0x0
PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )
The range is from 1 to 4.
3:2
/
/
/
1:0
R/W
0x0
PLL_FACTOR_M.
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