Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 93
PLL Factor M. (M=Factor + 1)
The range is from 1 to 4.
4.3.5.2. PLL_Audio Control Register (Default Value: 0x00035514)
Offset: 0x0008
Register Name: PLL_AUDIO_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
PLL_ENABLE.
0: Disable
1: Enable.
The PLL is for Audio.
PLL _AUDIO = (24MHz*N)/(M*P)
PLL_AUDIO(8X)= (24MHz*N*2)/M
PLL_AUDIO(4X)=PLL_AUDIO(8X)/2
PLL_AUDIO(2X)=PLL_AUDIO(4X)/2
The PLL output clock must be in the range of 20MHz~200MHz.
Its default is 24.571MHz.
30:29
/
/
/
28
R
0x0
LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
27:25
/
/
/
24
R/W
0x0
PLL_SDM_EN.
0: Disable
1: Enable
In this case, the PLL_FACTOR_N only low 4 bits are valid (N: The range is
from 1 to 16).
23:20
/
/
/
19:16
R/W
0x3
PLL_POSTDIV_P.
Post-div factor (P= Factor+1)
The range is from 1 to 16.
15
/
/
/
14:8
R/W
0x55
PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
……
Factor=127, N=128
7:5
/
/
/
4:0
R/W
0x14
PLL_PREDIV_M.
PLL Pre-div Factor(M = Factor+1).
The range is from 1 to 32.
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