Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 95
The range is from 1 to 16.
4.3.5.4. PLL_VE Control Register (Default Value: 0x03006207)
Offset: 0x0018
Register Name: PLL_VE_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
PLL_ENABLE.
0: Disable
1: Enable
In the integer mode, The PLL Output = (24MHz*N)/M.
In the fractional mode, the PLL Output is select by bit 25.
Note: The PLL output clock must be in the range of 30MHz~600MHz.
Its default is 297MHz.
30:29
/
/
/
28
R
0x0
LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
27:26
/
/
/
25
R/W
0x1
FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be set
to 0); No meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output =297MHz
24
R/W
0x1
PLL_MODE_SEL.
0: Fractional Mode
1: Integer Mode
Note: When in Fractional mode, the Per Divider M should be set to 0.
23:21
/
/
/
20
R/W
0x0
PLL_SDM_EN.
0: Disable
1: Enable
19:15
/
/
/
14:8
R/W
0x62
PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3
……
Factor=31, N=32
…
Factor=127, N=128
7:4
/
/
/
3:0
R/W
0x7
PLL_PREDIV_M.
PLL Pre Divider (M = Factor+1).
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