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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 96
The range is from 1 to 16.
4.3.5.5. PLL_DDR Control Register (Default Value: 0x00001000)
Offset: 0x0020
Register Name: PLL_DDR_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
PLL_ENABLE.
0: Disable
1: Enable
Set bit20 to validate the PLL after this bit is set to 1.
The PLL Output = (24MHz*N*K)/M.
Note: the PLL output clock must be in the range of 200MHz~2.6GHz.
Its default is 408MHz.
30:29
/
/
/
28
R
0x0
LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
27:25
/
/
/
24
R/W
0x0
PLL_SDM_EN.
0: Disable
1: Enable
23:21
/
/
/
20
R/W
0x0
PLL_DDR_CFG_UPDATE.
PLL_DDR Configuration Update.
When PLL_DDR has been changed, this bit should be set to 1 to validate the
PLL, otherwise the change would be invalid. And this bit would be cleared
automatically after the PLL change is valid.
0: No effect
1: Validating the PLL_DDR
19:13
/
/
/
12:8
R/W
0x10
PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3
……
Factor=31, N=32
7:6
/
/
/
5:4
R/W
0x0
PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )
The range is from 1 to 4.
3:2
/
/
/
1:0
R/W
0x0
PLL_FACTOR_M.
PLL Factor M.(M = Factor + 1 )
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