Owners manual
System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 99
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3
……
Factor=127, N=128
7:4
/
/
/
3:0
R/W
0x7
PLL_PRE_DIV_M.
PLL Pre Divider (M = Factor+1).
The range is from 1 to 16.
4.3.5.8. PLL_PERIPH1 Control Register (Default Value: 0x00041811)
Offset: 0x0044
Register Name: PLL_PERIPH1_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
PLL_ENABLE.
0: Disable
1: Enable
The PLL Output = 24MHz*N*K/2 .
Note: The PLL Output should be fixed to 600MHz, it is not recommended to
vary this value arbitrarily.
In the Clock Control Module, PLL(2X) output= PLL*2 = 24MHz*N*K.
The PLL output clock must be in the range of 200MHz~1.8GHz.
Its default is 600MHz.
30:29
/
/
/
28
R
0x0
LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
27:26
/
/
/
25
R/W
0x0
PLL_BYPASS_EN.
PLL Output Bypass Enable.
0: Disable
1: Enable
If the bypass is enabled, the PLL output is 24MHz.
24
R/W
0x0
PLL_CLK_OUT_EN.
PLL clock output enable.
0: Disable
1: Enable
23:21
/
/
/
20
R/W
0x0
PLL_SDM_EN.
0: Disable
1: Enable
19
/
/
/
18
R/W
0x1
PLL_24M_OUT_EN.
PLL 24MHz Output Enable.
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