User's Manual
Table Of Contents
- Description
- Features
- Ordering Information
- Absolute Maximum Ratings
- Electrical Specifications
- Typical Performance Graphs
- Pin Assignments
- Pin Descriptions
- Module Pin Assignments
- Module Dimensions
- Theory of Operation
- Module Description
- Overview
- Addressing Modes
- Automatic Addressing
- Address Register Use
- Acknowledgements and Assured Delivery
- Frequency Hopping Spread Spectrum
- Compatibility with the 250 Series
- Networking
- Transmitting Packets
- Receiving Packets
- Using the Buffer Empty (BE) Line
- Exception Engine
- Carrier Sense Multiple Access (CSMA)
- Using the Command Response (CRESP) Line
- Using the CMD Line
- AES Encryption
- Using the MODE_IND Line
- Using the PB Line
- Restore Factory Defaults
- Using the Low Power Features
- Baud Rate and Transmitter Output Power
- The Command Data Interface
- Reading from Registers
- Writing to Registers
- Command Length Optimization
- Example Code for Encoding Read/Write Commands
- The Command Data Interface Command Set
- Typical Applications
- Usage Guidelines for FCC Compliance
- Additional Testing Requirements
- Information to the user
- Product Labeling
- FCC RF Exposure Statement
- Antenna Selection
- Power Supply Requirements
- Antenna Considerations
- Interference Considerations
- Pad Layout
- Castellation Version Reference Design
- Microstrip Details
- Board Layout Guidelines
- Helpful Application Notes from Linx
- Production Guidelines
- Hand Assembly
- Automated Assembly
- General Antenna Rules
- Common Antenna Styles
- Regulatory Considerations
- Notes
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60 61
ENCRC - CRC Enable
Volatile Address = 0x53; Non-Volatile Address = 0x08
The protocol includes a Cyclic Redundancy Check (CRC) on the received
unencrypted packets to make sure that there are no errors. Encrypted
packets use a key-based error detection method. Any packets with errors
are discarded and not output on the UART. This feature can be disabled
if it is desired to perform error checking outside the module. Set the
ENCRC register to 0x01 to enable CRC checking, or 0x00 to disable it. The
default CRC mode setting is enabled. Figure 53 shows examples of the
commands and Figure 54 shows the available values.
Although disabling CRC checking allows receiving packets with errors
in the payload, errors in the header can still prevent packets from being
output by the module.
HumPRO-A
TM
Series CRC Enable Register Settings
V Mode
0x00 CRC Disabled
0x01 CRC Enabled
Figure 53: HumPRO-A
TM
Series CRC Enable Command and Response
Figure 54: HumPRO-A
TM
Series CRC Enable Register Settings
HumPRO-A
TM
Series CRC Enable
Read Command Read Response
Header Size Escape Address ACK Address Value
0xFF 0x02 0xFE
0x53
0x08
0x06
0x53
0x08
V
Write Command
Header Size Address Value
0xFF 0x02
0x53
0x08
V
BCTRIG - UART Byte Count Trigger
Volatile Address = 0x54; Non-Volatile Address = 0x09
The BCTRIG register determines the UART buffer level that triggers
the transmission of a packet. The minimum value is decimal 1 and the
maximum value is 192. The default value for this register is 64, which
provides a good mix of throughput and latency. At the maximum data rate,
a value of 128 optimizes throughput. This register does not guarantee a
particular transmission unit size; rather, it specifies the minimum desired
size. If there is not enough time left in the channel dwell time before the
module must hop to the next channel, for instance, the protocol engine
sends as many characters as it can to fill the current channel dwell time,
and sends the remaining characters on the next channel. Figure 55 shows
examples of the commands.
This trigger can be overridden by enabling the TXPKT option (PKTOPT
register, bit 0).
Figure 55: HumPRO-A
TM
Series UART Byte Count Trigger Command and Response
HumPRO-A
TM
Series UART Byte Count Trigger
Read Command Read Response
Header Size Escape Address ACK Address Value
0xFF 0x02 0xFE
0x54
0x09
0x06
0x54
0x09
V
Write Command
Header Size Address Value
0xFF 0x02
0x54
0x09
V