User's Manual

BSM-700 Specification Page 18/31 2014/03/31
LTC Network Access Confidential
5 Notes on operation
5.1 Power-on Sequence
We recommend that the power supplies are all powered at the same time.
5.2 IO State at Reset and Recommended Termination Handling
The RESET# pin is an active low reset. Assert the reset signal for a period >5ms to ensure a full reset. The RESET
# pin is pulled down internally until the power on, then the pull switches to a strong pull up.
Pin Name / Group
I/O Type
Full Chip Reset
USB_DP
Digital bidirectional
N/A
USB_DN
Digital bidirectional
N/A
UART_RX
Digital bidirectional with PU
Strong PU
UART_TX Digital bidirectional with PU Weak PU
SPI_CS#
Digital input with
PU
Strong PU
SPI_CLK
Digital input with PD
Weak PD
SPI_MISO
Digital tristate output with PD
Weak PU
SPI_MOSI
Digital input with PD
Weak PD
I2S_OUT Digital bidirectional with PD Weak PD
I2S_SYNC
Digital bidirectional with PD
Weak PD
I2S_BCLK
Digital b
idirectional with PD
Weak PD
RST#
Digital input with PU
Strong PU
PIO[15:0]
Digital bidirectional with PD
Weak PD
FLASH_IO[3:0]
Digital bidirectional with PD
Strong PD
FLASH_CS#
Digital bidirectional with PU
Strong PU
FLASH_CLK
Digital bidirectional w
ith PD
Strong PD