User's Manual

COMPANY CONFIDENTIAL
32
8.2.3 GPIO Assignments
GPIO Assignments for J3 64-pin Low Density Connector
GPIO
PIN Name
PIN Number
Function
00
MIICRS
61
Free
01
MIICOL
62
Free
03
MIITXCLK
55
iPOD Access Power
04
PDOUT0
47
Factory Reset
05
VCO0
49
IR Input
06
PDOUT1
45
Host NIREQ
08
SSMD4
50
E_GPIO_SDO/TBA
09
SSMD5
48
E_GPIO_SDI/TBA
10
SSMD6
56
E_GPIO_CLK/TBA
11
SSMD7
37
E_GPIO_NCS/TBA
13
AV3CTRL0
41
I2C_SCL
14
AV3CTRL1
39
I2C_SDA
15
NWAIT
15
Free
17
NCS3
33
Free
19
NCS2
17
IPOD NDETECT
Note: Not all 20 GPIO signals are brought out to J3 64-pin low density connector. For the CX870-3K, GPIOs 00,
01 and 03 are not brought out to J3 64-pin low density connector. J3 pin numbers 61, 62 and 55 are not
connected to any signal in the CX870-3K module.
9 Application Guidelines
9.1 Power Supply sequencing and Reset Timing
There are strict power sequencing and reset timing requirements.
 Power up the I/O voltage (3.3V) first and hold NRESET_MOD low.
 The core voltage (1.2V) must never be higher than (I/O voltage +0.5 V).
 The core voltage (1.2V) must be within the specified core voltage limits less than 300ms after the I/O voltage (3.3V)
reaches the specified I/O voltage limits.
 Throughout the power down process, the 3.3V supply must maintain a higher voltage than the 1.2V supply, until both
have reached ground potential.
 To assure a proper IC reset, the power supplies must be present for a minimum time of 2ms before NRESET_MOD is
de-asserted.
Please see the power and reset timing figure in Section 9.1.1 below.
About 1.9V, the arrival of 1.9V supply should lag behind the arrival of the 3.3V. The delay between the 1.9V and the 3.3V is
not critical. Typical delay is approximately 10ms, for example using 10kohm resistor and 0.1uF capacitor on the enable pin
of a 1.9V dc-to-dc converter.